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 PD - 96897
AUTOMOTIVE MOSFET
Features
Process Technology Low On-Resistance l175C Operating Temperature lFast Switching lRepetitive Avalanche Allowed up to Tjmax
lAdvanced lUltra
IRFR1010Z IRFU1010Z
HEXFET(R) Power MOSFET
D
VDSS = 55V RDS(on) = 7.5m
Description
Specifically designed for Automotive applications, this HEXFET(R) Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175C junction operating temperature, fast switching speed and improved repetitive avalanche rating . These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. Absolute Maximum Ratings
Parameter
G S
ID = 42A
D-Pak IRFR1010Z
Max.
91 65 42 360 140 0.9 20
I-Pak IRFU1010Z
Units
A
ID @ T C = 25C Continuous Drain Current, V GS @ 10V (Silicon Limited) ID @ T C = 100C Continuous Drain Current, V GS @ 10V ID @ T C = 25C IDM Continuous Drain Current, V GS @ 10V (Package Limited) Pulsed Drain Current
P D @T C = 25C Power Dissipation V GS E AS (Tested ) IAR E AR TJ T STG Linear Derating Factor Gate-to-Source Voltage
W W/C V mJ A mJ
E AS (Thermally limited) Single Pulse Avalanche Energyd Single Pulse Avalanche Energy Tested Value Avalanche CurrentA Repetitive Avalanche Energy Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting Torque, 6-32 or M3 screw
h
110 220 See Fig.12a, 12b, 15, 16 -55 to + 175
g
C 300 (1.6mm from case ) 10 lbfyin (1.1Nym)
Thermal Resistance
R JC R JA R JA Junction-to-Case
j
Parameter
Typ.
Max.
1.11 40 110
Units
C/W
Junction-to-Ambient (PCB mount) Junction-to-Ambient
j
ij
--- --- ---
HEXFET(R) is a registered trademark of International Rectifier.
www.irf.com
1
9/29/04
IRFR/U1010Z
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Coss Coss Coss eff. Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance
Min. Typ. Max. Units
55 --- --- 2.0 31 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 0.051 5.8 --- --- --- --- --- --- 63 17 23 17 76 42 48 4.5 7.5 2840 470 250 1630 360 560 --- --- 7.5 4.0 --- 20 250 200 -200 95 --- --- --- --- --- --- --- nH --- --- --- --- --- --- --- pF ns nC nA V m V S A
Conditions
VGS = 0V, ID = 250A VGS = 10V, ID = 42A VDS = 25V, ID = 42A VDS = 55V, VGS = 0V VDS = 55V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V ID = 42A VDS = 44V VGS = 10V VDD = 28V ID = 42A RG = 7.6 VGS = 10V
V/C Reference to 25C, ID = 1mA VDS = VGS, ID = 100A
e
e e
Between lead, 6mm (0.25in.) from package and center of die contact VGS = 0V VDS = 25V = 1.0MHz
G
D
S
VGS = 0V, VDS = 1.0V, = 1.0MHz VGS = 0V, VDS = 44V, = 1.0MHz VGS = 0V, VDS = 0V to 44V
f
Source-Drain Ratings and Characteristics
Parameter
IS ISM VSD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- --- --- --- --- 24 20 42 A 360 1.3 36 30 V ns nC
Conditions
MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25C, IS = 42A, VGS = 0V TJ = 25C, IF = 42A, VDD = 28V di/dt = 100A/s
e
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRFR/U1010Z
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
100
100
BOTTOM
BOTTOM
10
10
4.5V
4.5V 1 0.1 1
60s PULSE WIDTH
Tj = 25C 1 100 0.1 1 10
60s PULSE WIDTH
Tj = 175C 10 100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
Gfs , Forward Transconductance (S)
120 100 80 60 40 20 0 0 20 40 60 80 100 ID,Drain-to-Source Current (A) TJ = 25C
ID, Drain-to-Source Current()
100 TJ = 175C 10
TJ = 175C
1
TJ = 25C VDS = 25V
VDS = 10V 380s PULSE WIDTH
0.1 2 4
60s PULSE WIDTH 6 8 10
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
Fig 4. Typical Forward Transconductance vs. Drain Current
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3
IRFR/U1010Z
5000 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd
20
VGS, Gate-to-Source Voltage (V)
ID= 42A VDS = 44V VDS= 28V VDS= 11V
4000
16
C, Capacitance(pF)
3000
Ciss
12
2000
8
1000
Coss Crss
4
0
10 100
0 1
0
20
40
60
80
100
VDS , Drain-to-Source Voltage (V)
QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
1000.00
10000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA LIMITED BY R DS (on)
ISD , Reverse Drain Current (A)
100.00 TJ = 175C 10.00
1000
100
100sec 1msec 10msec Tc = 25C Tj = 175C Single Pulse 1 10 VDS , Drain-toSource Voltage (V)
10
1.00
TJ = 25C VGS = 0V 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VSD , Source-to-Drain Voltage (V)
1
0.10
0.1
DC 100
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRFR/U1010Z
100 LIMITED BY PACKAGE 80
ID , Drain Current (A)
RDS(on) , Drain-to-Source On Resistance (Normalized)
2.5
ID = 42A
2.0
VGS = 10V
60
1.5
40
20
1.0
0 25 50 75 100 125 150 175 TC , Case Temperature (C)
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (C)
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 10. Normalized On-Resistance vs. Temperature
10
Thermal Response ( Z thJC )
1
D = 0.50 0.20
0.1
0.10 0.05 0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE )
J J 1
R1 R1 2
R2 R2
R3 R3 3 C 3
Ri (C/W) i (sec) 0.3854 0.000251 0.3138 0.4102 0.001092 0.015307
1
2
0.01
Ci= i/Ri Ci i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.01 0.1
0.001 1E-006 1E-005 0.0001 0.001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFR/U1010Z
EAS, Single Pulse Avalanche Energy (mJ)
15V
500
VDS
L
DRIVER
400
ID 7.6A 11A BOTTOM 42A
TOP
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
300
A
0.01
200
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
100
0 25 50 75 100 125 150 175
Starting TJ, Junction Temperature (C)
I AS
Fig 12b. Unclamped Inductive Waveforms
QG
Fig 12c. Maximum Avalanche Energy vs. Drain Current
10 V
QGS
QGD
VGS(th) Gate threshold Voltage (V)
4.0
VG
3.5
ID = 1.0mA ID = 100A
ID = 250A
3.0
Charge
Fig 13a. Basic Gate Charge Waveform
2.5
2.0
L
0
1.5
DUT 1K
VCC
1.0 -75 -50 -25 0 25 50 75 100 125 150 175
TJ , Temperature ( C )
Fig 13b. Gate Charge Test Circuit
Fig 14. Threshold Voltage vs. Temperature
6
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IRFR/U1010Z
1000
Duty Cycle = Single Pulse
100
Avalanche Current (A)
0.01
10
0.05 0.10
Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25C due to avalanche losses
1
0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
120
EAR , Avalanche Energy (mJ)
100
TOP Single Pulse BOTTOM 1% Duty Cycle ID = 42A
80
60
40
20
0 25 50 75 100 125 150
Starting TJ , Junction Temperature (C)
Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 15, 16). tav = Average time in avalanche. 175 D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 16. Maximum Avalanche Energy vs. Temperature
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7
IRFR/U1010Z
Driver Gate Drive
D.U.T
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
RD
VDS VGS RG 10V
Pulse Width 1 s Duty Factor 0.1 %
D.U.T.
+
-VDD
Fig 18a. Switching Time Test Circuit
VDS 90%
10% VGS
td(on) tr t d(off) tf
Fig 18b. Switching Time Waveforms
8
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IRFR/U1010Z
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 6.45 (.245) 5.68 (.224) 10.42 (.410) 9.40 (.370) 0.51 (.020) MIN. LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 3X 2X 1.14 (.045) 0.76 (.030) 0.89 (.035) 0.64 (.025) 0.25 (.010) M AMB NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 4.57 (.180) 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). 0.58 (.023) 0.46 (.018) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018)
6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 1 2 3 -B1.52 (.060) 1.15 (.045)
2.28 (.090)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: THIS IS AN IRFR120 WITH AS SEMBLY LOT CODE 1234 ASS EMBLED ON WW 16, 1999 IN THE AS SEMBLY LINE "A"
N ote: "P" in ass embly line pos ition indicates "Lead-Free"
INTERNATIONAL RECTIFIER LOGO AS SEMBLY LOT CODE
PART NUMBER
IRFR120 12 916A 34
DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A
OR
INTERNAT IONAL RECT IFIER LOGO ASS EMBLY LOT CODE PART NUMBER
IRFR120 12 P916A 34
DATE CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 1999 WEEK 16 A = ASS EMBLY SITE CODE
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9
IRFR/U1010Z
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 6.45 (.245) 5.68 (.224) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 0.58 (.023) 0.46 (.018) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN
1.52 (.060) 1.15 (.045) 1 -B2.28 (.090) 1.91 (.075) 2 3
6.22 (.245) 5.97 (.235)
NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 9.65 (.380) 8.89 (.350) 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006).
3X
1.14 (.045) 0.76 (.030)
3X
0.89 (.035) 0.64 (.025) M AMB
1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018)
2.28 (.090) 2X
0.25 (.010)
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFU120 WIT H AS S EMBLY LOT CODE 5678 AS S EMBLED ON WW 19, 1999 IN T HE AS SEMBLY LINE "A" Note: "P" in ass embly line pos ition indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER
IRFU120 919A 56 78
DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A
OR
INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER
IRFU120 56 78
DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 19 A = AS S EMBLY S ITE CODE
10
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IRFR/U1010Z
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR TRR TRL
16.3 ( .641 ) 15.7 ( .619 )
16.3 ( .641 ) 15.7 ( .619 )
12.1 ( .476 ) 11.9 ( .469 )
FEED DIRECTION
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481.
Repetitive rating; pulse width limited by
Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . max. junction temperature. (See fig. 11). Limited by TJmax, starting TJ = 25C, L = 0.13mH Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive RG = 25, IAS = 42A, VGS =10V. Part not avalanche performance. recommended for use above this value. This value determined from sample failure population. 100% Pulse width 1.0ms; duty cycle 2%. tested to this value in production. When mounted on 1" square PCB (FR-4 or G-10 Material) . For recommended footprint and soldering techniques refer to application note #AN-994 R is measured at TJ approximately 90C Data and specifications subject to change without notice. This product has been designed for the Automotive [Q101] market. Qualification Standards can be found on IR's Web site.
Notes:
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.9/04
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11


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